URMP Projects

MCECS Undergraduate Research and Mentoring Program (URMP) Student Projects in teuscher.:Lab

Useful info:

Projects:

Below is a list of current projects (in no particular order). All of them have room for several students.

Project 1:

  • Title: 3D FPGA Cell Matrix by Self-assembly
  • Topics: 3D, FPGA, architecture, reconfiguration, self-assembly
  • Description: To overcome physical size limitations in Moore’s law scaling of transistors in inherently two-dimensional geometries, efforts are being directed at wafer stacking to implement more quasi three dimensional (3D) architectures. However, significant and unprecedented gains in terms of packing and speed can be achieved if CMOS components can be integrated in truly 3D cellular porous architectures. This project combines cross-disciplinary expertise in software and hardware to create prototype 3D cellular computational devices by self-assembly. We propose to study the creation of electronic devices based on the paradigm of self-assembling smart modules in 3D crystals. The interdisciplinary approach combines cutting-edge chemistry with CMOS technology and novel communication and computing paradigms. For this project, our approach is to utilize commercial off-the shelf IC circuits to construct a 3D FPGA Cell Matrix prototype as a proof-of-concept. While our approach is rooted in the 3D integration of chips, the software and hardware assembly approaches that will be developed are relevant across length scales from chips to transistors. Our ideas are based on strong preliminary results, an interdisciplinary approach and the ability to address all problems as they relate to software, hardware architecture, assembly, defect tolerance and cooling.

Project 2:

  • Title: Optimization of Hierarchical and Heterogeneous Network-on-Chip (NoC) Architectures
  • Topics: NoC, network, hierarchical, architecture
  • Description: The goal of this project is to optimize hierarchical and heterogeneous 3D Network-on-Chip (NoC) architectures with long-range links. This will allow to find non-classical interconnect architectures for multi-core chips by drawing inspiration from natural complex networks that minimize resource consumption while optimizing relevant performance metrics, such as latency, throughput, power and area overhead. We will apply metaheuristic algorithms to find optimal solutions. The existing C++ CNEA simulation framework will be expanded to handle 3D heterogeneous architectures.

Project 3:

  • Title: Biomolecular Computation
  • Topics: DNA, molecular, computation
  • Description: Molecular computing is a promising computational paradigm, in which computational functions are evaluated at the nanoscale, with potential applications in smart molecular diagnostics and therapeutics. However, despite recent advances in the field, prospects for direct application of these techniques to solve real-world problems are limited by the lack of robust interfaces between molecular computers and biological and chemical systems. The goal of this project is to model and simulate new molecular computing systems that are capable of adaptive, bio-inspired behavior, such as dynamic learning and adaptation.

Project 4:

  • Title: Computation with Emerging Nanodevice Networks
  • Topics: nanodevices, memristor, computation, network
  • Description:

    State-of-the-art inference models (IMs) learn their deep network structure directly from their sensory inputs, yielding sparse approximations that enable high-performance target detection and tracking. The goal of this project is to explore emerging memristor-based architectures for image processing.  Memristors will be used as the associative memory in neurons to perform lookup, storage, and compute-in-memory.

Project 5:

  • Title: Modeling and Simulation of Randomly Assembled Nanowire Networks
  • Topics: nanowires, self-assembly, modeling, simulation
  • Description: Advancements in CMOS technology have demonstrated the scaling of a single transistor down to a few nanometers. The smaller the transistors, the faster they operate. However, this does not hold true for chip interconnects. The wire delay and the resistance increases as the process technology scales down. Hence, new and promising interconnect paradigms are required to address these challenges. Moreover, networks will likely be irregular in their topologies having new fabrication techniques like self-assembly. This is because we lack control over such processes. Hence new and innovative approaches are needed to be introduced to address these challenges. Carbon Nanotubes (CNTs) and nanowires are promising candidates for new interconnects. The main goal of this project is to propose new models for self-assembled nanowire networks and to evaluate their performance and properties.

Project 6

  • Title: Approximate computation with emerging devices
  • Topics: approximate, computation, devices, memristors, nonlinear
  • Description: Approximate computation is a new trend that explores and harnesses trade-offs between the precision and energy/power consumption of computing systems. The goal of this project is to design and implement approximate computing systems based on emerging devices, such as memristors.

Project 7

  • Title: Unified English Braille through a Powerful and Responsive eLearning Platform (UEB PREP)
  • Topics: braille, software, platform
  • Description: Project Unified English Braille through a Powerful and Responsive eLearning Platform (UEB PREP) will design and develop an evidence-based Unified English Braille (UEB) eLearning platform to serve a target population of adult braille users, parents of children who are visually impaired, and professionals (trained and pre-service) who work with individuals who are blind and visually impaired. Depending  on the skill-set and interest, the student can get involved in implementing the platform on the web, on iOS, or Android.

What URMP students have to say:

Next Generation Computing Models and Architectures